1. Technical Field
This disclosure relates generally to improved embedded semiconductor products and methods and apparatus for making such semiconductor products.
2. Related Art
An embedded semiconductor device such as a Flash memory may include, among other things, a memory core and a number of logic gates to control operations that act upon the memory core (e.g., read, write, and erase operations). Combining the memory core and the logic gates of a Flash memory into a single integrated circuit (IC) has historically required relatively expensive, time consuming, and difficult manufacturing processes.
The difficulty in combining the memory core and the logic gates in a single IC stems, at least in part, from the fact that the memory components require different dimensions from the logical gate component. Typically, to achieve the different dimensions, the manufacture of a memory core employs different manufacturing steps than the manufacturing of the logic gates. For instance, the memory core of a Flash memory includes a number of wordlines (WL) that are relatively wide, but spaced very closely together—WLs can be separated by a gap that is smaller than the resolution limit of lithography in some cases. To achieve this small gap between WLs, Flash memory production methods may require the use of a spacer, which is generally not used during the production of other semiconductor components. By contrast, logic gates are preferably thinner, narrower, and spaced further apart than the WL structures better suited for the memory core. To achieve the required dimensions for logical gate structures, a trim process is frequently employed during the manufacturing process. The trim and spacer processes used in the manufacture of the logic gates and the memory, respectively, cannot be performed simultaneously and must, therefore, be performed sequentially in most applications.
Since the use of a spacer and the trim method are largely incompatible with one another, Flash memory producers have had to use separate patterning processes for the memory core and logical gate portions of a Flash memory IC. That is, current methods might pattern the core wordlines using, for instance, a standard mask/etch/mask/etch sequence with a spacer used to define the core and then subsequently pattern the logic using a mask trim. This sequential patterning of the core and logic adds to the time, expense, and difficulty of manufacturing embedded semiconductors such as Flash memory ICs. Accordingly, there is a need for methods and apparatus that facilitate simultaneous manufacturing of semiconductors, such as, but not limited to, Flash memory, that comprise components that are generally subject to different manufacturing process steps.